236 search results - page 44 / 48 » Chordal Topologies for Interconnection Networks |
ANCS
2009
ACM
13 years 5 months ago
2009
ACM
Torus, mesh, and flattened butterfly networks have all been considered as candidate architectures for on-chip interconnection networks. In this paper, we study the problem of opti...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
CCGRID
2006
IEEE
14 years 1 months ago
2006
IEEE
A problem with running distributed shared memory applications in heterogeneous environments is that making optimal use of available resources often requires significant changes t...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
—This paper describes a new low-power, area and pin efficient alternative to differential encoding for high performance chip-to-chip and backplane signaling. The technique, calle...
IPPS
2003
IEEE
14 years 25 days ago
2003
IEEE
The dual-cube is a newly proposed topology for interconnection networks, which uses low dimensional hypercubes as building blocks. The primary advantages of the dual-cube over the...