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ISLPED
1995
ACM
114views Hardware» more  ISLPED 1995»
13 years 11 months ago
Power and area optimization by reorganizing CMOS complex gate circuits
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
M. Tachibana, S. Kurosawa, R. Nojima, Norman Kojim...
ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 5 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards
MST
2010
121views more  MST 2010»
13 years 6 months ago
Entropy of Operators or why Matrix Multiplication is Hard for Depth-Two Circuits
We consider unbounded fanin depth-2 circuits with arbitrary boolean functions as gates. We define the entropy of an operator f : {0, 1}n → {0, 1}m as the logarithm of the maximu...
Stasys Jukna
COCO
2001
Springer
107views Algorithms» more  COCO 2001»
14 years 6 days ago
In Search of an Easy Witness: Exponential Time vs. Probabilistic Polynomial Time
Restricting the search space {0, 1}n to the set of truth tables of “easy” Boolean functions on log n variables, as well as using some known hardness-randomness tradeoffs, we ...
Russell Impagliazzo, Valentine Kabanets, Avi Wigde...
GLVLSI
2008
IEEE
150views VLSI» more  GLVLSI 2008»
13 years 7 months ago
Using unsatisfiable cores to debug multiple design errors
Due to the increasing complexity of today's circuits a high degree of automation in the design process is mandatory. The detection of faults and design errors is supported qu...
André Sülflow, Görschwin Fey, Rod...