A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths

Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This paper presents a complete synthesis flow that generates self-timed combinational networks from conventional Boolean networks. The Boolean network is partitioned into small function blocks which are then synthesised using selftimed techniques. The procedure employs relaxation optimisations to distribute the overheads associated with selftimed networks between function-blocks. Relaxation is incorporated into the function block synthesis procedures, meaning the optimisations can be applied at a much finer granularity than previously possible. The new techniques are demonstrated on a range of benchmarks showing average reduction of 5% in area, 26% in latency and 48% in energy over gate-level relaxation techniques and 17% in area, 8% in latency and 20% in energy consumption over other block-level relaxation techniques...

• Type: Journal
• Year: 2010
• Where: ACSD
• Authors: W. B. Toms, David A. Edwards
• Keywords: ACSD 2010, Boolean Network, Function Block, Hardware, Relaxation Techniques