Sciweavers

983 search results - page 59 / 197
» Circuit Complexity and Multiplicative Complexity of Boolean ...
Sort
View
ICALP
2010
Springer
14 years 9 days ago
From Secrecy to Soundness: Efficient Verification via Secure Computation
d Abstract) Benny Applebaum1 , Yuval Ishai2 , and Eyal Kushilevitz3 1 Computer Science Department, Weizmann Institute of Science 2 Computer Science Department, Technion and UCLA 3 ...
Benny Applebaum, Yuval Ishai, Eyal Kushilevitz
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
14 years 9 days ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
COCO
2009
Springer
106views Algorithms» more  COCO 2009»
14 years 5 months ago
Improved Approximation of Linear Threshold Functions
We prove two main results on how arbitrary linear threshold functions f(x) = sign(w · x − θ) over the n-dimensional Boolean hypercube can be approximated by simple threshold f...
Ilias Diakonikolas, Rocco A. Servedio
IFIP
2001
Springer
14 years 2 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 7 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici