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PATMOS
2005
Springer
14 years 1 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
DAC
2005
ACM
13 years 9 months ago
Spatially distributed 3D circuit models
Spatially distributed 3D circuit models are extracted with a segmentto-segment BEM (Boundary Element Method) algorithm for both capacitance and inverse inductance couplings rather...
Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byr...
FPGA
2005
ACM
215views FPGA» more  FPGA 2005»
14 years 1 months ago
Design, layout and verification of an FPGA using automated tools
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spent on circuit design, layout and verification. It currently takes approximately ...
Ian Kuon, Aaron Egier, Jonathan Rose
EH
2000
IEEE
84views Hardware» more  EH 2000»
13 years 11 months ago
Evolutionary Design of Single Electron Systems
The differences between electronics design through artificial evolution and through conventional methods have the consequence that evolved circuits may take unusual leverage from ...
Adrian Thompson, Christoph Wasshuber
ECBS
2003
IEEE
84views Hardware» more  ECBS 2003»
14 years 29 days ago
Model-Integrated Design Toolset for Polymorphous Computer-Based Systems
Polymorphous computer-based systems are systems in which the CPU architecture “morphs” or changes shape to meet the requirements of the application. Optimized and efficient de...
Brandon Eames, Ted Bapty, Ben Abbott, Sandeep Neem...