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IPPS
1994
IEEE
15 years 8 months ago
Parallel Evaluation of a Parallel Architecture by Means of Calibrated Emulation
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
Henk L. Muller, Paul W. A. Stallard, David H. D. W...
128
Voted
RTCSA
2000
IEEE
15 years 8 months ago
Efficient resource management for hard real-time communication over differentiated services architectures
We propose an efficient strategy for resource management for scalable QoS guaranteed real-time communication services. This strategy is based on sink trees, and is particularly we...
Byung-Kyu Choi, Riccardo Bettati
ISCA
1997
IEEE
93views Hardware» more  ISCA 1997»
15 years 8 months ago
The Energy Efficiency of IRAM Architectures
Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more en...
Richard Fromm, Stylianos Perissakis, Neal Cardwell...
ICML
1994
IEEE
15 years 8 months ago
A Modular Q-Learning Architecture for Manipulator Task Decomposition
Compositional Q-Learning (CQ-L) (Singh 1992) is a modular approach to learning to performcomposite tasks made up of several elemental tasks by reinforcement learning. Skills acqui...
Chen K. Tham, Richard W. Prager
CASES
2008
ACM
15 years 6 months ago
Predictable programming on a precision timed architecture
In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function ...
Ben Lickly, Isaac Liu, Sungjun Kim, Hiren D. Patel...