The Energy Efficiency of IRAM Architectures

Portable systems demand energy efficiency in order to maximize battery life. IRAM architectures, which combine DRAM and a processor on the same chip in a DRAM process, are more energy efficient than conventional systems. The high density of DRAM permits a much larger amount of memory on-chip than a traditional SRAM cache design in a logic process. This allows most or all IRAM memory accesses to be satisfied on-chip. Thus there is much less need to drive high-capacitance off-chip buses, which contribute significantly to the energy consumption of a system. To quantify this advantage we apply models of energy consumption in DRAM and SRAM memories to results from cache simulations of applications reflective of personal productivity tasks on low power systems. We find that IRAM memory hierarchies consume as little as 22% of the energy consumed by a conventional memory hierarchy for memoryintensive applications, while delivering comparable performance. Furthermore, the energy consumed by a ...

• Type: Conference
• Year: 1997
• Where: ISCA
• Authors: Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos E. Kozyrakis, Bruce McGaughy, David A. Patterson, Thomas E. Anderson, Katherine A. Yelick
• Keywords: DRAM, Hardware, IRAM Memory, ISCA 1997, Memory Hierarchy