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TVLSI
2008
187views more  TVLSI 2008»
15 years 4 months ago
A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors
During the last years, the growing application complexity, design, and mask costs have compelled embedded system designers to increasingly consider partially reconfigurable applica...
Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Che...
INFOCOM
1998
IEEE
15 years 8 months ago
Implementing Distributed Packet Fair Queueing in a Scalable Switch Architecture
To support the Internet's explosive growth and expansion into a true integrated services network, there is a need for cost-effective switching technologies that can simultaneo...
Donpaul C. Stephens, Hui Zhang
191
Voted
ANCS
2008
ACM
15 years 6 months ago
Low power architecture for high speed packet classification
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
Alan Kennedy, Xiaojun Wang, Zhen Liu, Bin Liu
151
Voted
CASES
2008
ACM
15 years 6 months ago
Efficiency and scalability of barrier synchronization on NoC based many-core architectures
Interconnects based on Networks-on-Chip are an appealing solution to address future microprocessor designs where, very likely, hundreds of cores will be connected on a single chip...
Oreste Villa, Gianluca Palermo, Cristina Silvano
ISARCS
2010
240views Hardware» more  ISARCS 2010»
15 years 6 months ago
Engineering a Distributed e-Voting System Architecture: Meeting Critical Requirements
Voting is a critical component of any democratic process; and electronic voting systems should be developed following best practices for critical system development. E-voting has i...
J. Paul Gibson, Eric Lallet, Jean-Luc Raffy