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CONEXT
2007
ACM
15 years 8 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
153
Voted
EXPCS
2007
15 years 8 months ago
Empirical performance assessment using soft-core processors on reconfigurable hardware
Simulation has been the de facto standard method for performance evaluation of newly proposed ideas in computer architecture for many years. While simulation allows for theoretica...
Richard Hough, Praveen Krishnamurthy, Roger D. Cha...
FPL
2006
Springer
211views Hardware» more  FPL 2006»
15 years 8 months ago
Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description
Field programmable gate arrays (FPGAs), graphics processing units (GPUs) and Sony's PlayStation 2 vector units offer scope for hardware acceleration of applications. We compa...
Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckm...
HOLOMAS
2005
Springer
15 years 10 months ago
Simulation of Underwater Surveillance by a Team of Autonomous Robots
Within this paper we describe a simulation environment for the underwater surveillance and propose architecture of control part of autonomous robot capable of efficient operation i...
Milan Rollo, Petr Novák, Pavel Jisl
136
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ISCAS
2005
IEEE
191views Hardware» more  ISCAS 2005»
15 years 10 months ago
Behavioural modeling and simulation of a switched-current phase locked loop
Recent work has shown that the use of switched current methods can provide an effective route to implementation of analog IC functionality using a standard digital CMOS process. Fu...
Peter R. Wilson, Reuben Wilcock