3395 search results - page 506 / 679 » Circuit-aware architectural simulation |
166
Voted
CP
2000
Springer
15 years 10 months ago
2000
Springer
Abstract. This paper describes the architecture and implementation of a constraint-based framework for rapid prototyping of distributed applications such as virtual simulations, co...
154
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EH
1999
IEEE
15 years 10 months ago
1999
IEEE
MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reco...
159
Voted
ICMCS
1999
IEEE
15 years 10 months ago
1999
IEEE
This paper presents design and architecture of the distributed virtual reality service (dvr) which allows collaboration-unaware VRML animations and simulations to be integrated in...
144
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IPPS
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper we propose a simple extension to the I/O architecture of scalable multiprocessors that optimizes page swap-outs significantly. More specifically, we propose the use o...
127
Voted
ISCAS
1999
IEEE
15 years 10 months ago
1999
IEEE
A general high-Q biquad lter architecture capable of operating in the GHz range is proposed and analyzed. This lter, which is usable in bandpass and lowpass applications, utilizes...