ISCAS 1999 - PDF Preprint Papers

ISCAS 1999 International Symposium on Circuits and Systems

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ISCAS
1999
IEEE

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Ripple correlation control, with some applications

14 years 3 months ago

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Ripple correlation control is a nonlinear control approach applicable to power electronic circuits. It makes use of voltage, current, or power ripple and correlates this with swit...

P. T. Krein

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Id	Views	Title	Status

1	300	Ripple correlation control, with some applications	claim
2	220	Area-optimized FPGA implementation of a digital FM modulator	claim
3	206	Transimpedance amplifier with differential photodiode current sensing	claim
4	177	Obtaining digital gradient signals for analog adaptive filters	claim
5	161	New microwave bandstop filter using lumped and transversal network	claim
6	149	A comparison of fractal dimension algorithms using synthetic and experimental data	claim
7	146	Optimization of CMOS MEMS microwave power sensors	claim
8	145	Fast FPGA-based pipelined digit-serial/parallel multipliers	claim
9	142	Behavioral synthesis of asynchronous systems: a methodology	claim
10	134	Low power DCT implementation approach for VLSI DSP processors	claim
11	133	Peer group filtering and perceptual color image quantization	claim
12	132	Dynamic trellis diagrams for optimized DSP code generation	claim
13	132	Complex discriminative learning Bayesian neural equalizer	claim
14	131	A multilevel modulation scheme for high-speed wireless infrared communications	claim
15	129	A tunable triode-MOSFET transconductor and its application to gm-C filters	claim
16	129	Fuzzy logic damping controller for FACTS devices in interconnected power systems	claim
17	128	Dynamic scheduling of multiple video objects for MPEG-4 encoding with user interactions	claim
18	126	Synthesis of multiple-input translinear element networks	claim
19	126	Applications of clone circuits to issues in physical-design	claim
20	124	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity	claim
21	124	On the robustness of vector set partitioning image coders to bit errors	claim
22	124	CMOS cryptosystem using a Lorenz chaotic oscillator	claim
23	122	A time-varying Prony method for instantaneous frequency estimation at low SNR	claim
24	122	Convergence properties of mixed-norm algorithms under general error criteria	claim
25	122	A class of complementary IIR filters	claim
26	121	The linear time-varying approach applied to a first-order dynamic translinear filter	claim
27	120	Vector median-rational hybrid filters for multichannel image processing	claim
28	119	A SPICE model for simulating the impedance-frequency characteristics of high frequency PIN switching diodes	claim
29	118	Critical quantization decisions in transform coding and blocking artifacts	claim
30	116	A coefficient segmentation algorithm for low power implementation of FIR filters	claim
31	116	Analysis of noise in higher-order translinear filters	claim
32	115	Novel high-radix residue number system multipliers and adders	claim
33	114	Channel equalization by feedforward neural networks	claim
34	114	Nonuniformly offset polyphase synthesis of a bandpass signal from complex-envelope samples	claim
35	114	Multicarrier QAM modulator	claim
36	114	Auditory cortical spectral shape analysis in analog VLSI	claim
37	113	Energy efficient software through dynamic voltage scheduling	claim
38	112	An acoustic-phonetic feature-based system for automatic phoneme recognition in continuous speech	claim
39	111	Joint transcoding of multiple MPEG video bitstreams	claim
40	110	Noise-tolerant dynamic circuit design	claim
41	110	Receiver-based congestion control mechanism for Internet video transmission	claim
42	109	Solution of vector partial differential equations by transfer function models	claim
43	106	A low power scheduling scheme with resources operating at multiple voltages	claim
44	106	Multi-objective design strategy for high-level low power design of DSP systems	claim
45	106	Test pattern generation for width compression in BIST	claim
46	106	High speed multistage CMOS clock buffers with pulse width control loop	claim
47	106	Adaptive minimax filtering via recursive optimal quadratic approximations	claim
48	106	Repeater insertion in RLC lines for minimum propagation delay	claim
49	105	Configuration self-test in FPGA-based reconfigurable systems	claim
50	105	Dynamical phasors in modeling and control of active filters	claim
51	104	Controlling an integrator through data networks: stability in the presence of unknown time-variant delays	claim
52	102	Power and signal integrity improvement in ultra high-speed current mode logic	claim
53	102	Capacitor mismatch error cancellation technique for a successive approximation A/D converter	claim
54	102	An asynchronous data recovery/retransmission technique with foreground DLL calibration	claim
55	101	Modeling of accumulation MOS capacitors for analog design in digital VLSI processes	claim
56	100	Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis	claim
57	100	Real-time H.263+ frame rate control for low bit rate VBR video	claim
58	100	The state space framework for blind dynamic signal extraction and recovery	claim
59	99	CMOS gate modeling based on equivalent inverter	claim
60	98	Exact analysis of second order bandpass delta-sigma modulator with sinusoidal inputs	claim
61	97	Monaural separation of independent acoustical components	claim
62	95	VLSI circuits with fractal layout for spatial image decorrelation	claim
63	95	Evaluating iterative improvement heuristics for bigraph crossing minimization	claim
64	94	Design of symmetric orthonormal wavelet filters using a single complex allpass filter	claim
65	94	Tensor-product wavelet vs. Mallat decomposition: a comparative analysis	claim
66	94	Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI	claim
67	94	Designing system on a chip products using systems engineering tools	claim
68	94	Correct diagnosis of almost all faulty units in a multiprocessor system	claim
69	93	Design of a lower-error fixed-width multiplier for speech processing application	claim
70	93	Problems of computing Lyapunov exponents in power electronics	claim
71	93	Probability distribution of the switching intervals in chaotic pulse streams-a comparative study	claim
72	92	A high precision CMOS current mirror/divider	claim
73	92	Hybrid inverse halftoning using adaptive filtering	claim
74	92	A standard target decoder model for MPEG-4 FlexMux streams	claim
75	90	A 1.2 V NPN-only log-domain integrator	claim
76	90	Stability of two-dimensional discrete systems	claim
77	88	Theory and design of causal stable IIR PR cosine-modulated filter banks	claim
78	88	An implantable mixed analog/digital neural stimulator circuit	claim
79	88	Signal waveform characterization in RLC trees	claim
80	87	Instruction level power model of microcontrollers	claim
81	87	Asymptotical optimality of DFT based DMT transceivers	claim
82	87	A novel high gain, high bandwidth CMOS differential front-end for wireless optical systems	claim
83	87	Analysis of subsystem integration in aircraft power distribution systems	claim
84	86	An algorithm for the verification of timing diagrams realizability	claim
85	86	Design of high-performance CMOS charge pumps in phase-locked loops	claim
86	85	A tunable, video-frequency, low-power, single-amplifier biquadratic filter in CMOS	claim
87	85	Low power full-search block-matching motion estimation chip for H.263+	claim
88	85	Equivalence classes of clone circuits for physical-design benchmarking	claim
89	84	Motion-compensated frame interpolation scheme for H.263 codec	claim
90	82	Regular symmetric arrays for non-symmetric functions	claim
91	82	Discrete fractional Hadamard transform	claim
92	82	Synthesis of low coefficient sensitivity digital filters using genetic programming	claim
93	82	VLSI architecture and design for high performance adaptive video scaling	claim
94	82	Transform domain neural filters	claim
95	81	A CMOS continuous-time active biquad filter for gigahertz-band applications	claim
96	81	Lost transform domain data concealment in GenLOT based coders	claim
97	81	Theoretical expectation value of the capacity of fuzzy polynomial bidirectional hetero-correlator	claim
98	81	Nonlinear signal processor design: a building block approach	claim
99	80	A universal CMOS voltage interface circuit	claim
100	80	A chaotic network based on intermittently coupled capacitors	claim
101	80	A harmonic balance approach to bifurcation analysis of limit cycles	claim
102	79	Energy minimization of system pipelines using multiple voltages	claim
103	79	Lossless multi channel predictive coding for images	claim
104	78	Cost-effective low-power architectures of video coding systems	claim
105	78	An area-efficient analog VLSI architecture for state-parallel Viterbi decoding	claim
106	77	Power reduction through iterative gate sizing and voltage scaling	claim
107	77	A low-voltage translinear second-order quadrature oscillator	claim
108	77	A data embedding scheme for H.263 compatible video coding	claim
109	77	Fast compression artifact reduction technique based on nonlinear filtering	claim
110	76	2-V 900-MHz quadrature coupled LC oscillators with improved amplitude and phase matchings	claim
111	76	Fast motion estimation using modified circular zonal search	claim
112	75	Wavelet based watermarking method for digital images using the human visual system	claim
113	74	A low-power switched-current algorithmic A/D converter	claim
114	74	Mismatch-shaping serial digital-to-analog converter	claim
115	74	Adaptive multi-channel prediction for lossless scalable coding	claim
116	73	Correlation learning rule in floating-gate pFET synapses	claim
117	72	Shape-based sequential machine analysis	claim
118	72	Observing test response of embedded cores through surrounding logic	claim
119	72	An efficient RF power transfer and bidirectional data transmission to implantable electronic devices	claim
120	71	A novel analog-digital flash converter architecture based on capacitive threshold gates	claim
121	71	A new architecture for computationally adaptive full-search block-matching motion estimation	claim
122	70	A new multipath amplifier design technique for enhancing gain without sacrificing bandwidth	claim
123	70	On optimization of filter banks with denoising applications	claim
124	70	Multirate single-stage and multistage structures for high-speed recursive digital filtering	claim
125	70	Rate-distortion constrained quadtree segmentation for stereoscopic video coding	claim
126	69	Improving performance of high precision signal processing algorithms on programmable DSPs	claim
127	69	A new method in FIR filter design	claim
128	68	High performance multirate SC circuits with predictive correlated double sampling technique	claim
129	68	Fully parallel on-chip learning hardware neural network for real-time control	claim
130	67	High speed interface for system-on-chip design by self-tested self-synchronization	claim
131	66	Low energy register allocation beyond basic blocks	claim
132	65	Low-overhead error-resilient bit-plane image coding	claim
133	64	Convergence analysis results for the class of affine projection algorithms	claim
134	64	Efficient implementation of parallel correlators for code acquisition in DS/CDMA systems	claim
135	63	Investigating speaker features from very short speech records	claim
136	63	Passive device modeling methodology using nonlinear optimization	claim
137	63	Interference reduction in nerve cuff electrode recordings-a new approach	claim
138	62	Analysis of nonlinear dynamic arrays, through spatial mode decomposition	claim
139	62	From circuits to spectral peaks	claim
140	61	High-performance BiCMOS output buffer design strategies	claim
141	61	A transformation for computational latency reduction in turbo-MAP decoding	claim
142	61	Robust video segmentation employing variable bandwidth object boundary	claim
143	59	Chaotic itinerancy phenomena on coupled n-double scrolls chaotic circuits	claim
144	58	Design of nonlinear-phase FIR digital filters: a semidefinite programming approach	claim
145	58	Restoration of three dimensional microscopic images using the row action projection method	claim

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