3395 search results - page 549 / 679 » Circuit-aware architectural simulation |
156
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ICS
2004
Tsinghua U.
15 years 9 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
170
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IPPS
2003
IEEE
15 years 9 months ago
2003
IEEE
We discuss here a parallel implementation of the visualisation of data from a galaxy formation simulation within the Triana problem-solving environment. The visualisation is a tes...
120
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DAC
2007
ACM
16 years 4 months ago
2007
ACM
It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. An important design constraint in suc...
147
Voted
PPOPP
2010
ACM
16 years 1 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
129
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ISCA
2009
IEEE
15 years 10 months ago
2009
IEEE
Analysis of technology and application trends reveals a growing imbalance in the peak compute-to-memory-capacity ratio for future servers. At the same time, the fraction contribut...