Abstract—Packet delay traces are important measurements for analyzing end-to-end performance and for designing traffic control algorithms in computer networks. Due to the fact t...
We present an evaluation strategy for clock synchronization algorithms. It is based on a combination of measured traces, which provide for realistic performance estimation, and of...
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
A cellular automaton (CA) is a parallel synchronous computing model, which consists in a juxtaposition of finite automata (cells) whose state evolves according to that of their ne...