Delay-Insensitive Cell Matrix

This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement regular digital circuits or new types of circuits for nanocomputing systems. One advantage of this cell matrix compared to its synchronous counterpart is the delay-insensitive asynchronous nature. This architecture does not need a global clock, which would be infeasible for nanocomputing systems due to the enormous number of clocked nodes. Instead, a hand-shaking protocol for inter-component communication is implemented. Keywords-parallel processing; asynchronous; delay-insensitive; clockless; NCL

• Type: Journal
• Year: 2010
• Where: CDES
• Authors: Scott Smith, David Roclin, Jia Di
• Keywords: CDES 2010, Cell Matrix, Delay-insensitive Asynchronous Nature, Hardware, Regular Digital Circuits