96 search results - page 12 / 20 » Clock-Aware Placement for FPGAs |
FPL
2005
Springer
14 years 27 days ago
2005
Springer
This paper addresses exploitation of the capabilities of platform FPGAs to implement embedded networking for systems on chip. In particular, a methodology for exploring trade-offs...
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The development of Field Programmable Gate Arrays (FPGAs) had tremendous improvements in the last few years. They were extended from simple logic circuits to complex Systems-on-Ch...
FPGA
2003
ACM
14 years 18 days ago
2003
ACM
Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we ...
FPGA
2003
ACM
14 years 18 days ago
2003
ACM
To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand p...
FPGA
2001
ACM
13 years 12 months ago
2001
ACM
As integrated circuits are migrated to more advanced technologies, it has become clear that crosstalk is an important physical phenomenon that must be taken into account. Crosstal...