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DAC
2000
ACM
14 years 8 months ago
Multiple Si layer ICs: motivation, performance analysis, and design implications
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. Semiconductor Industry Association (SIA) roadmap predicts that, beyond the ...
Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, ...
ISCAS
2008
IEEE
118views Hardware» more  ISCAS 2008»
14 years 1 months ago
Low-power IC design for a wireless BCI system
—Integrated circuit (IC) design for a wireless BCI system is put forward in this paper. The system is composed of an electrode, a stimulator, antennas, and an integrated circuit ...
Ming Liu, Hong Chen, Run Chen, Zhihua Wang
ISQED
2003
IEEE
96views Hardware» more  ISQED 2003»
14 years 21 days ago
New DFM Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
Pradiptya Ghosh, Chung-shin Kang, Michael Sanie, D...
VLSID
2006
IEEE
169views VLSI» more  VLSID 2006»
14 years 1 months ago
A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology
As the IC process technology scales, the oxide thickness and operating voltage continues to decrease. The gate oxide thickness in recent and future IC process technology has appro...
Sanjeev K. Jain, Pankaj Agarwal
DAC
2005
ACM
14 years 8 months ago
OPERA: optimization with ellipsoidal uncertainty for robust analog IC design
As the d esig n-m anu factu ring interface becom es increasing ly com plicated with IC technolog y scaling , the correspond ing process variability poses g reat challeng es for na...
Yang Xu, Kan-Lin Hsiung, Xin Li, Ivan Nausieda, St...