169 search results - page 30 / 34 » Co-Scheduling Hardware and Software Pipelines |
151
click to vote
CODES
2008
IEEE
15 years 11 months ago
2008
IEEE
The combination of flit-buffer flow control methods and latency-insensitive protocols is an effective solution for networks-on-chip (NoC). Since they both rely on backpressure...
149
click to vote
HIPEAC
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
163
click to vote
CGO
2003
IEEE
15 years 9 months ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
145
click to vote
CASES
2003
ACM
15 years 9 months ago
2003
ACM
Knowing the Worst-Case Execution Time (WCET) of a program is necessary when designing and verifying real-time systems. A correct WCET analysis method must take into account the po...
133
click to vote
CASES
2006
ACM
15 years 8 months ago
2006
ACM
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...