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ASPLOS
1987
ACM
13 years 11 months ago
Machine-Independent Virtual Memory Management for Paged Uniprocessor and Multiprocessor Architectures
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting...
Richard F. Rashid, Avadis Tevanian, Michael Young,...
IPPS
1997
IEEE
13 years 11 months ago
External Adjustment of Runtime Parameters in Time Warp Synchronized Parallel Simulators
Several optimizations to the Time Warp synchronization protocol for parallel discrete event simulation have been proposed and studied. Many of these optimizations have included so...
Radharamanan Radhakrishnan, Lantz Moore, Philip A....
LCTRTS
2007
Springer
14 years 1 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
ANCS
2007
ACM
13 years 11 months ago
Compiling PCRE to FPGA for accelerating SNORT IDS
Deep Payload Inspection systems like SNORT and BRO utilize regular expression for their rules due to their high expressibility and compactness. The SNORT IDS system uses the PCRE ...
Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan
CCS
2010
ACM
13 years 7 months ago
BLADE: an attack-agnostic approach for preventing drive-by malware infections
Web-based surreptitious malware infections (i.e., drive-by downloads) have become the primary method used to deliver malicious software onto computers across the Internet. To addr...
Long Lu, Vinod Yegneswaran, Phillip A. Porras, Wen...