Sciweavers

1225 search results - page 231 / 245
» Code Compression for Embedded Systems
Sort
View
SCOPES
2004
Springer
14 years 23 days ago
An Integer Linear Programming Approach to Classify the Communication in Process Networks
New embedded signal processing architectures are emerging that are composed of loosely coupled heterogeneous components like CPUs or DSPs, specialized IP cores, reconfigurable uni...
Alexandru Turjan, Bart Kienhuis, Ed F. Deprettere
DATE
2002
IEEE
123views Hardware» more  DATE 2002»
14 years 11 days ago
False Path Elimination in Quasi-Static Scheduling
We have developed a technique to compute a Quasi Static Schedule of a concurrent specification for the software partition of an embedded system. Previous work did not take into a...
G. Arrigoni, L. Duchini, Claudio Passerone, Lucian...
ICCD
1999
IEEE
110views Hardware» more  ICCD 1999»
13 years 11 months ago
TriMedia CPU64 Architecture
We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a...
Jos T. J. van Eijndhoven, Kees A. Vissers, Evert-J...
CIKM
1999
Springer
13 years 11 months ago
Rule-Based Query Optimization, Revisited
We present the architecture and a performance assessment of an extensible query optimizer written in Venus. Venus is a general-purpose active-database rule language embedded in C+...
Lane Warshaw, Daniel P. Miranker
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
13 years 11 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...