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SIGMETRICS
2003
ACM
199views Hardware» more  SIGMETRICS 2003»
14 years 28 days ago
Data cache locking for higher program predictability
Caches have become increasingly important with the widening gap between main memory and processor speeds. However, they are a source of unpredictability due to their characteristi...
Xavier Vera, Björn Lisper, Jingling Xue
ISCA
2010
IEEE
284views Hardware» more  ISCA 2010»
14 years 23 days ago
Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address
Phase change memory (PCM) is an emerging memory technology for future computing systems. Compared to other non-volatile memory alternatives, PCM is more matured to production, and...
Nak Hee Seong, Dong Hyuk Woo, Hsien-Hsin S. Lee
EUROCRYPT
2010
Springer
14 years 14 days ago
Encryption Schemes Secure against Chosen-Ciphertext Selective Opening Attacks
Imagine many small devices send data to a single receiver, encrypted using the receiver’s public key. Assume an adversary that has the power to adaptively corrupt a subset of the...
Serge Fehr, Dennis Hofheinz, Eike Kiltz, Hoeteck W...
ADC
1999
Springer
97views Database» more  ADC 1999»
13 years 12 months ago
Pseudo-Naive Evaluation
We introduce pseudo-naive evaluation, a method for execution of mixed top-down/bottom-up logic programs and deductive databases. The method is intermediate in power between naive ...
Donald A. Smith, Mark Utting
ASPLOS
1989
ACM
13 years 11 months ago
Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor
A very long instruction word (VLIW) processorexploits parallelism by controlling multiple operations in a single instruction word. This paper describes the architecture and compil...
Robert Cohn, Thomas R. Gross, Monica S. Lam, P. S....