Sciweavers

966 search results - page 118 / 194
» Code Generation for Embedded Processors
Sort
View
SAC
2004
ACM
14 years 2 months ago
L0 buffer energy optimization through scheduling and exploration
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
Murali Jayapala, Tom Vander Aa, Francisco Barat, G...
PLDI
2006
ACM
14 years 2 months ago
Automatic instruction scheduler retargeting by reverse-engineering
In order to generate high-quality code for modern processors, a compiler must aggressively schedule instructions, maximizing resource utilization for execution efficiency. For a ...
Matthew J. Bridges, Neil Vachharajani, Guilherme O...
ICDT
2001
ACM
147views Database» more  ICDT 2001»
14 years 1 months ago
Parallelizing the Data Cube
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambr...
GPCE
2009
Springer
14 years 1 months ago
A generative programming approach to developing pervasive computing systems
Developing pervasive computing applications is a difficult task because it requires to deal with a wide range of issues: heterogeneous devices, entity distribution, entity coordi...
Damien Cassou, Benjamin Bertran, Nicolas Loriant, ...
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 9 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...