Sciweavers

966 search results - page 44 / 194
» Code Generation for Embedded Processors
Sort
View
CASES
2009
ACM
14 years 3 months ago
CGRA express: accelerating execution using dynamic operation fusion
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
Yongjun Park, Hyunchul Park, Scott A. Mahlke
HICSS
2000
IEEE
110views Biometrics» more  HICSS 2000»
14 years 1 months ago
Reverse Compilation for Digital Signal Processors: A Working Example
We describe the implementation and use of a reverse compiler from Analog Devices 21xx assembler source to ANSI-C with optional use of the language extensions for the TMS320C6x pr...
Adrian Johnstone, Elizabeth Scott, Tim Womack
CODES
2005
IEEE
14 years 2 months ago
Retargetable generation of TLM bus interfaces for MP-SoC platforms
In order to meet flexibility, performance and energy efficiency constraints, future SoC (System-on-Chip) designs will contain an increasing number of heterogeneous processor cor...
Andreas Wieferink, Rainer Leupers, Gerd Ascheid, H...
ECRTS
2005
IEEE
14 years 2 months ago
Automated Model-Based Generation of Ravenscar-Compliant Source Code
Graphical languages of various sorts are increasingly used for the specification and the design of high-integrity real-time systems. Their coverage however does not extend with a...
Matteo Bordin, Tullio Vardanega
CC
2003
Springer
192views System Software» more  CC 2003»
14 years 2 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...