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DASIP
2010
13 years 3 months ago
Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation
This paper proposes an automatic design flow from userfriendly design to efficient implementation of video processing systems. This design flow starts with the use of coarsegrain ...
Ruirui Gu, Jonathan Piat, Mickaël Raulet, J&o...
ARCS
2009
Springer
14 years 3 months ago
Evaluating CMPs and Their Memory Architecture
Abstract. Many-core processor architectures require scalable solutions that reflect the locality and power constraints of future generations of technology. This paper presents a CM...
Chris R. Jesshope, Mike Lankamp, Li Zhang
FPL
2009
Springer
172views Hardware» more  FPL 2009»
14 years 1 months ago
Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors
Automated code generation and performance tuning techniques for concurrent architectures such as GPUs, Cell and FPGAs can provide integer factor speedups over multi-core processor...
Nachiket Kapre, André DeHon
CODES
2005
IEEE
13 years 10 months ago
Implementation of dynamic streaming Applications on heterogeneous multi-Processor architectures
System design based on static task graphs does not match well with modern consumer electronic devices with dynamic stream processing applications. We propose the TTL API for task ...
Tomas Henriksson, Jeffrey Kang, Pieter van der Wol...
DAC
2005
ACM
14 years 9 months ago
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design
In many of embedded systems, particularly for those with high data computations, the delay of memory access is one of the major bottlenecks in the system's performance. It ha...
Jungeun Kim, Taewhan Kim