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» Code Transformations to Improve Memory Parallelism
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ICPPW
2006
IEEE
14 years 2 months ago
Retargeting Image-Processing Algorithms to Varying Processor Grain Sizes
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
Sam Sander, Linda M. Wills
CORR
2010
Springer
198views Education» more  CORR 2010»
13 years 8 months ago
Space and the Synchronic A-Ram
Space is a spatial programming language designed to exploit the massive parallelism available in a formal model of computation called the Synchronic A-Ram, and physically related ...
Alexander Victor Berka
DCC
2005
IEEE
14 years 8 months ago
Efficient Inter-Band Prediction and Wavelet Based Compression for Hyperspectral Imagery: A Distributed Source Coding Approach
Hyperspectral images have correlation at the level of pixels; moreover, images from neighboring frequency bands are also closely correlated. In this paper, we propose to use distr...
Caimu Tang, Ngai-Man Cheung, Antonio Ortega, Cauli...
TCAD
2008
127views more  TCAD 2008»
13 years 8 months ago
Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozor...
CGO
2008
IEEE
14 years 3 months ago
Compiling for vector-thread architectures
Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the ...
Mark Hampton, Krste Asanovic