272 search results - page 6 / 55 » Code Transformations to Improve Memory Parallelism |
IPPS
1999
IEEE
14 years 26 days ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
PPOPP
2010
ACM
14 years 5 months ago
2010
ACM
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
With the increasing gap between processor speed and memory latency, the performance of data-dominated programs are becoming more reliant on fast data access, which can be improved...
IEEEPACT
1999
IEEE
14 years 26 days ago
1999
IEEE
The performance of applications on large shared-memory multiprocessors with coherent caches depends on the interaction between the granularity of data sharing, the size of the coh...
PLDI
1995
ACM
14 years 3 days ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...