135 search results - page 15 / 27 » Code and Data Transformations for Improving Shared Cache Per... |
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
CAINE
2006
13 years 8 months ago
2006
The synergy of software and hardware leads to efficient application expression profile (AEP) not only in terms of execution time and energy but also optimal architecture usage. We...
ICPP
1999
IEEE
13 years 11 months ago
1999
IEEE
There has been much work recently on improving the locality performance of loop nests in scientific programs through the use of loop as well as data layout optimizations. However,...
IWMM
2011
Springer
12 years 10 months ago
2011
Springer
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...