Sciweavers

135 search results - page 18 / 27
» Code and Data Transformations for Improving Shared Cache Per...
Sort
View
CC
2010
Springer
190views System Software» more  CC 2010»
14 years 2 months ago
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?
On Chip Multiprocessors (CMP), it is common that multiple cores share certain levels of cache. The sharing increases the contention in cache and memory-to-chip bandwidth, further h...
Yunlian Jiang, Eddy Z. Zhang, Kai Tian, Xipeng She...
ASPLOS
1992
ACM
13 years 11 months ago
Design and Evaluation of a Compiler Algorithm for Prefetching
Software-controlled data prefetching is a promising technique for improving the performance of the memory subsystem to match today's high-performance processors. While prefet...
Todd C. Mowry, Monica S. Lam, Anoop Gupta
ISPASS
2008
IEEE
14 years 1 months ago
Pinpointing and Exploiting Opportunities for Enhancing Data Reuse
—The potential for improving the performance of data-intensive scientific programs by enhancing data reuse in cache is substantial because CPUs are significantly faster than me...
Gabriel Marin, John M. Mellor-Crummey
IPCCC
1999
IEEE
13 years 11 months ago
Measurement, analysis and performance improvement of the Apache Web server
Performance of Web servers is critical to the success of many corporations and organizations. However, very few results have been published that quantitatively study the server be...
Yiming Hu, Ashwini K. Nanda, Qing Yang
IPPS
1999
IEEE
13 years 11 months ago
A Graph Based Framework to Detect Optimal Memory Layouts for Improving Data Locality
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...