31 search results - page 3 / 7 » Code generation schema for modulo scheduled loops |
ICS
1995
Tsinghua U.
14 years 3 days ago
1995
Tsinghua U.
In this paper we give a new run–time technique for finding an optimal parallel execution schedule for a partially parallel loop, i.e., a loop whose parallelization requires syn...
CODES
2006
IEEE
14 years 8 days ago
2006
IEEE
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
IPPS
1998
IEEE
14 years 24 days ago
1998
IEEE
An effort to formalize the process of software pipelining loops with conditions is presented in this paper. A formal framework for scheduling such loops, based on representing set...
CGO
2004
IEEE
14 years 9 days ago
2004
IEEE
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to the outer loops. In a companion paper, we proposed a ...
PPOPP
2009
ACM
14 years 9 months ago
2009
ACM
Recent advances in polyhedral compilation technology have made it feasible to automatically transform affine sequential loop nests for tiled parallel execution on multi-core proce...