133 search results - page 22 / 27 » Code restructuring for improving cache performance of MPSoCs |
ASPLOS
2012
ACM
12 years 4 months ago
2012
ACM
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to para...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...
ASPLOS
2009
ACM
14 years 9 months ago
2009
ACM
Miss rate curves (MRCs) are useful in a number of contexts. In our research, online L2 cache MRCs enable us to dynamically identify optimal cache sizes when cache-partitioning a s...
IPPS
2007
IEEE
14 years 2 months ago
2007
IEEE
— We consider memory subsystem optimizations for improving the performance of sparse scientific computation while reducing the power consumed by the CPU and memory. We first co...
RTAS
2010
IEEE
13 years 7 months ago
2010
IEEE
—Hardware-managed caches introduce large amounts of timing variability, complicating real-time system design. One alternative is a memory system with scratchpad memories which im...