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ICS
1999
Tsinghua U.
14 years 1 months ago
Improving the performance of speculatively parallel applications on the Hydra CMP
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
Kunle Olukotun, Lance Hammond, Mark Willey
IFIP
1999
Springer
14 years 1 months ago
Frontier: A Fast Placement System for FPGAs
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...
Russell Tessier
GLVLSI
1998
IEEE
122views VLSI» more  GLVLSI 1998»
14 years 1 months ago
Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
With the increased clock frequency of modern, high-performance processors over 500 MHz, in some cases, limiting the power dissipation has become the most stringent design target. ...
Luca Benini, Giovanni De Micheli, Alberto Macii, E...
POPL
1994
ACM
14 years 25 days ago
Reducing Indirect Function call Overhead in C++ Programs
Modern computer architectures increasingly depend on mechanisms that estimate future control flow decisions to increase performance. Mechanisms such as speculative execution and p...
Brad Calder, Dirk Grunwald
DAC
2007
ACM
14 years 21 days ago
Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies
This paper presents MOJITO, a system which optimizes across thousands of analog circuit topologies simultaneously, and returns a set of sized topologies that collectively provide ...
Trent McConaghy, Pieter Palmers, Georges G. E. Gie...