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PCI
2005
Springer
14 years 2 months ago
Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
Evangelia Athanasaki, Kornilios Kourtis, Nikos Ana...
EUROPAR
2009
Springer
14 years 1 months ago
Distributed Data Partitioning for Heterogeneous Processors Based on Partial Estimation of Their Functional Performance Models
The paper presents a new data partitioning algorithm for parallel computing on heterogeneous processors. Like traditional functional partitioning algorithms, the algorithm assumes ...
Alexey L. Lastovetsky, Ravi Reddy
ICCAD
1997
IEEE
129views Hardware» more  ICCAD 1997»
14 years 25 days ago
A fast and robust exact algorithm for face embedding
We present a new matrix formulation of the face hypercube embedding problem that motivates the design of an efficient search strategy to find an encoding that satisfies all fac...
Evguenii I. Goldberg, Tiziano Villa, Robert K. Bra...
SIGGRAPH
1996
ACM
14 years 23 days ago
Linear-Time Dynamics Using Lagrange Multipliers
Current linear-time simulation methods for articulated figures are based exclusively on reduced-coordinate formulations. This paper describes a general, non-iterative linear-time ...
David Baraff
GECCO
2006
Springer
133views Optimization» more  GECCO 2006»
14 years 8 days ago
Evolutionary search for optimal combinations of markers in clothing manufacturing
Optimizing combinations of placements of parts, known as markers, is an important preparatory step in order-based industrial production of clothes. Given a work order in the form ...
Bogdan Filipic, Iztok Fister, Marjan Mernik