144 search results - page 15 / 29 » Combination Methods for Satisfiability and Model-Checking of... |
MODELS
2009
Springer
14 years 2 months ago
2009
Springer
A well known challenge in the formal methods domain is to improve their integration with practical engineering methods. In the context of embedded systems, model checking requires ...
TCAD
2010
13 years 2 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
CAV
2009
Springer
14 years 2 months ago
2009
Springer
Systems and Networks on Chips (NoCs) are a prime design focus of many hardware manufacturers. In addition to functional verification, which is a difficult necessity, the chip desi...
ISORC
1999
IEEE
13 years 12 months ago
1999
IEEE
We describe the design of VIP, a graphical front-end to the model checker SPIN. VIP supports a visual formalism, called v-Promela that connects the model checker to modern hierarc...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...