266 search results - page 4 / 54 » Combining Software and Hardware Verification Techniques |
TCAD
2010
13 years 4 months ago
2010
Abstract--Functional verification is one of the major bottlenecks in system-on-chip design due to the combined effects of increasing complexity and lack of automated techniques for...
DATE
1998
IEEE
14 years 2 months ago
1998
IEEE
We present a new combinational verification technique where the functional specification of a circuit under verification is utilized to simplify the verification task. The main id...
AC
2005
Springer
13 years 9 months ago
2005
Springer
The aim of this chapter is to give an overview of the theoretical foundation and the practical application of logic model checking techniques for the verification of multi-threade...
SIGSOFT
2007
ACM
14 years 10 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
ECBS
2010
IEEE
14 years 2 months ago
2010
IEEE
The complexity of software in embedded systems has increased significantly over the last years so that software verification now plays an important role in ensuring the overall pr...