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ATVA
2009
Springer
141views Hardware» more  ATVA 2009»
13 years 11 months ago
Formal Verification for High-Assurance Behavioral Synthesis
We present a framework for certifying hardware designs generated through behavioral synthesis, by using formal verification to certify the associated synthesis transformations. We ...
Sandip Ray, Kecheng Hao, Yan Chen, Fei Xie, Jin Ya...
POPL
1992
ACM
13 years 11 months ago
Abstract Semantics for a Higher-Order Functional Language with Logic Variables
Semantics for a Higher-Order Functional Language with Logic Variables Radha Jagadeesan Imperial College, London, UK SW7 2BZ. Keshav Pingali Cornell University, Ithaca, NY 14853. A...
Radha Jagadeesan, Keshav Pingali
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
ECAI
2006
Springer
13 years 11 months ago
Automatic Generation of Implied Constraints
Abstract. A well-known difficulty with solving Constraint Satisfaction Problems (CSPs) is that, while one formulation of a CSP may enable a solver to solve it quickly, a different ...
John Charnley, Simon Colton, Ian Miguel