46 search results - page 7 / 10 » Combining symbolic execution with model checking to verify p... |
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
SIGSOFT
2007
ACM
14 years 8 months ago
2007
ACM
Automated verification is a technique for establishing if certain properties, usually expressed in temporal logic, hold for a system model. The model can be defined using a high-l...
SP
2010
IEEE
13 years 11 months ago
2010
IEEE
—Fuzz testing has proven successful in finding security vulnerabilities in large programs. However, traditional fuzz testing tools have a well-known common drawback: they are in...
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
This paper considers the problem of formal verification of MPI programs operating under a fixed test harness for safety properties without building verification models. In our app...
ASPLOS
2011
ACM
12 years 11 months ago
2011
ACM
This paper presents S2E, a platform for analyzing the properties and behavior of software systems. We demonstrate S2E’s use in developing practical tools for comprehensive perfo...