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IPPS
2007
IEEE
14 years 1 months ago
Task-pushing: a Scalable Parallel GC Marking Algorithm without Synchronization Operations
This paper describes a scalable parallel marking technique for garbage collection that does not employ any synchronization operation. To achieve good scalability, two major design...
Ming Wu, Xiao-Feng Li
CF
2010
ACM
14 years 4 days ago
On-chip communication and synchronization mechanisms with cache-integrated network interfaces
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architect...
Stamatis G. Kavadias, Manolis Katevenis, Michail Z...
MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
13 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
CCGRID
2009
IEEE
14 years 1 months ago
Natively Supporting True One-Sided Communication in
As high-end computing systems continue to grow in scale, the performance that applications can achieve on such large scale systems depends heavily on their ability to avoid explic...
Gopalakrishnan Santhanaraman, Pavan Balaji, K. Gop...
CHARME
2001
Springer
117views Hardware» more  CHARME 2001»
13 years 11 months ago
A Higher-Level Language for Hardware Synthesis
We describe SAFL+: a call-by-value, parallel language in the style of ML which combines imperative, concurrent and functional programming. Synchronous channels allow communication ...
Richard Sharp, Alan Mycroft