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HPCA
2009
IEEE
16 years 5 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
158
Voted
INFOCOM
2012
IEEE
13 years 7 months ago
Network optimization for DHT-based applications
—P2P platforms have been criticized because of the heavy strain that some P2P services can inflict on costly interdomain links of network operators. It is therefore necessary to...
Yi Sun, Yang Richard Yang, Xiaobing Zhang, Yang Gu...
177
Voted
CCECE
2006
IEEE
15 years 10 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
140
Voted
SIGCOMM
2009
ACM
15 years 11 months ago
Optimizing the BSD routing system for parallel processing
The routing architecture of the original 4.4BSD [3] kernel has been deployed successfully without major design modification for over 15 years. In the unified routing architectur...
Qing Li, Kip Macy
132
Voted
SIGCOMM
2009
ACM
15 years 11 months ago
Crossbow: a vertically integrated QoS stack
This paper describes a new architecture which addresses Quality of Service (QoS) by creating unique flows for applications, services, or subnets. A flow is a dedicated and indep...
Sunay Tripathi, Nicolas Droux, Thirumalai Srinivas...