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» Compact FPGA implementations of QUAD
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EH
2003
IEEE
138views Hardware» more  EH 2003»
14 years 23 days ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
ESANN
2006
13 years 8 months ago
Parallel hardware implementation of a broad class of spiking neurons using serial arithmetic
Abstract. Current digital, directly mapped implementations of spiking neural networks use serial processing and parallel arithmetic. On a standard CPU, this might be the good choic...
Benjamin Schrauwen, Jan M. Van Campenhout
CVIU
2010
115views more  CVIU 2010»
13 years 7 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
ICES
2005
Springer
138views Hardware» more  ICES 2005»
14 years 1 months ago
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Kyrre Glette, Jim Torresen
PAIRING
2010
Springer
153views Cryptology» more  PAIRING 2010»
13 years 5 months ago
Compact Hardware for Computing the Tate Pairing over 128-Bit-Security Supersingular Curves
This paper presents a novel method for designing compact yet efficient hardware implementations of the Tate pairing over supersingular curves in small characteristic. Since such cu...
Nicolas Estibals