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» Comparative Evaluation of Two Scalable QoS Architectures
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MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 2 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
HPCA
1997
IEEE
14 years 1 days ago
Global Address Space, Non-Uniform Bandwidth: A Memory System Performance Characterization of Parallel Systems
Many parallel systems offer a simple view of memory: all storage cells are addresseduniformly. Despite a uniform view of the memory, the machines differsignificantly in theirmemo...
Thomas Stricker, Thomas R. Gross
CIKM
1999
Springer
14 years 3 days ago
Rule-Based Query Optimization, Revisited
We present the architecture and a performance assessment of an extensible query optimizer written in Venus. Venus is a general-purpose active-database rule language embedded in C+...
Lane Warshaw, Daniel P. Miranker
ICIP
2008
IEEE
14 years 9 months ago
Wavelet-based multi-view video coding with joint best basis wavelet packets
An approach to scalable multi-view video coding with joint best basis wavelet packets is examined in this paper. A 4-D wavelet transform is used to decorrelate the multi-view vide...
André Kaup, Béatrice Pesquet-Popescu...
IMC
2006
ACM
14 years 1 months ago
Shared-state sampling
We present an algorithm, Shared-State Sampling (S3 ), for the problem of detecting large flows in high-speed networks. While devised with different principles in mind, S3 turns ...
Frederic Raspall, Sebastià Sallent, Josep Y...