415 search results - page 44 / 83 » Comparative evaluation of memory models for chip multiproces... |
129
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CASES
2001
ACM
15 years 9 months ago
2001
ACM
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of loc...
162
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DSN
2002
IEEE
15 years 10 months ago
2002
IEEE
This paper examines the effect of technology scaling and microarchitectural trends on the rate of soft errors in CMOS memory and logic circuits. We describe and validate an end-to...
130
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DATE
2009
IEEE
16 years 16 days ago
2009
IEEE
This paper presents a novel technique for the modeling, simulation, and analysis of real-time applications on MultiProcessor Systems-on-Chip (MPSoCs). This technique is based on a...
175
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WWW
2005
ACM
16 years 6 months ago
2005
ACM
Design of high performance Web servers has become a recent research thrust to meet the increasing demand of networkbased services. In this paper, we propose a new Web server archi...
155
Voted
IEEEPACT
2005
IEEE
15 years 11 months ago
2005
IEEE
While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures sin...