415 search results - page 57 / 83 » Comparative evaluation of memory models for chip multiproces... |
CCGRID
2010
IEEE
13 years 8 months ago
2010
IEEE
Although shared memory programming models show good programmability compared to message passing programming models, their implementation by page-based software distributed shared m...
SIGOPS
2010
13 years 2 months ago
2010
Modern chip-level multiprocessors (CMPs) contain multiple processor cores sharing a common last-level cache, memory interconnects, and other hardware resources. Workloads running ...
CP
2003
Springer
14 years 25 days ago
2003
Springer
This work introduces a combinatorial optimization problem called Mars Express Memory Dumping Problem (Mex-Mdp), which arises in the European Space Agency program Mars Express. It c...
SAMOS
2004
Springer
14 years 29 days ago
2004
Springer
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
GLVLSI
2011
IEEE
12 years 11 months ago
2011
IEEE
This paper proposes a novel L1 data cache design with dualversioning SRAM cells (dvSRAM) for chip multi-processors (CMP) that implement optimistic concurrency proposals. In this n...