Scalable Instruction-Level Parallelism.

This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves as a replacement for outof-order instruction issue; it defines the model and explores implementations issues. The model results in a fully distributed implementation in which data is distributed to one register file per processor, which is scalable as the number of ports in each register file is constant. The only component with less than ideal scaling properties is the the switching network between processors. 1 Some Issues in Current Microprocessor Design Over the last twelve years Moore predicts a packing density increase of 256 in silicon die with a corresponding speed increase of 16. Whereas we see speed increases better than predicted, the same is not true of system-level concurrency. The history of the PPC processor (see http://www.rootvg.net/RSmodels.htm) shows that clock speed has increased at twi...

• Type: Conference
• Year: 2004
• Where: SAMOS
• Authors: Chris R. Jesshope
• Keywords: Packing Density, SAMOS 2004, Speed Increases, System-level Concurrency