Sciweavers

415 search results - page 9 / 83
» Comparative evaluation of memory models for chip multiproces...
Sort
View
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 8 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
SEUS
2009
IEEE
14 years 2 months ago
Towards Time-Predictable Data Caches for Chip-Multiprocessors
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
Martin Schoeberl, Wolfgang Puffitsch, Benedikt Hub...
IISWC
2006
IEEE
14 years 1 months ago
Modeling Cache Sharing on Chip Multiprocessor Architectures
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...
Pavlos Petoumenos, Georgios Keramidas, Håkan...
ICPP
2003
IEEE
14 years 25 days ago
Performance and Power Impact of Issue-width in Chip-Multiprocessor Cores
In chip-multiprocessors (CMPs), the number of cores and the issue width of each core presents an important design trade-off to balance the amount of TLP and ILP between multi-thre...
Magnus Ekman, Per Stenström
ISCA
2005
IEEE
181views Hardware» more  ISCA 2005»
14 years 1 months ago
Adaptive Mechanisms and Policies for Managing Cache Hierarchies in Chip Multiprocessors
With the ability to place large numbers of transistors on a single silicon chip, manufacturers have begun developing chip multiprocessors (CMPs) containing multiple processor core...
Evan Speight, Hazim Shafi, Lixin Zhang, Ramakrishn...