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SIGMETRICS
2011
ACM
178views Hardware» more  SIGMETRICS 2011»
12 years 10 months ago
Soft error benchmarking of L2 caches with PARMA
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
Jinho Suh, Mehrtash Manoochehri, Murali Annavaram,...
IPPS
2006
IEEE
14 years 1 months ago
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue
The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processo...
Jaume Abella, Antonio González
WOWMOM
2006
ACM
108views Multimedia» more  WOWMOM 2006»
14 years 1 months ago
Multimedia Correlation Analysis in Unstructured Peer-to-Peer Networks
Recent years saw the rapid development of peer-topeer (P2P) networks in a great variety of applications. However, similarity-based k-nearest-neighbor retrieval (k-NN) is still a c...
Bo Yang, Ali R. Hurson, Yu Jiao, Thomas E. Potok
ICS
2010
Tsinghua U.
14 years 4 days ago
Cache oblivious parallelograms in iterative stencil computations
We present a new cache oblivious scheme for iterative stencil computations that performs beyond system bandwidth limitations as though gigabytes of data could reside in an enormou...
Robert Strzodka, Mohammed Shaheen, Dawid Pajak, Ha...
VLDB
2001
ACM
149views Database» more  VLDB 2001»
13 years 11 months ago
Cache-Conscious Concurrency Control of Main-Memory Indexes on Shared-Memory Multiprocessor Systems
Recent research addressed the importance of optimizing L2 cache utilization in the design of main memory indexes and proposed the so-called cache-conscious indexes such as the CSB...
Sang Kyun Cha, Sangyong Hwang, Kihong Kim, Keunjoo...