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TJS
2008
95views more  TJS 2008»
15 years 5 months ago
Combating I-O bottleneck using prefetching: model, algorithms, and ramifications
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
Akshat Verma, Sandeep Sen
RTSS
2009
IEEE
16 years 10 hour ago
Multiprocessor Extensions to Real-Time Calculus
Abstract—Many embedded platforms consist of a heterogeneous collection of processing elements, memory modules, and communication subsystems. These components often implement diff...
Hennadiy Leontyev, Samarjit Chakraborty, James H. ...
ASPLOS
2004
ACM
15 years 10 months ago
An ultra low-power processor for sensor networks
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
Virantha N. Ekanayake, Clinton Kelly IV, Rajit Man...
ASAP
2005
IEEE
121views Hardware» more  ASAP 2005»
15 years 11 months ago
Using TLM for Exploring Bus-based SoC Communication Architectures
As billion transistor System-on-chips (SoC) become commonplace and design complexity continues to increase, designers are faced with the daunting task of meeting escalating design...
Sudeep Pasricha, Mohamed Ben-Romdhane
FM
2008
Springer
152views Formal Methods» more  FM 2008»
15 years 6 months ago
Constraint Prioritization for Efficient Analysis of Declarative Models
The declarative modeling language Alloy and its automatic analyzer provide an effective tool-set for building designs of systems and checking their properties. The Alloy Analyzer p...
Engin Uzuncaova, Sarfraz Khurshid