622 search results - page 92 / 125 » Comparing the Optimal Performance of Multiprocessor Architec... |
CASES
2008
ACM
13 years 10 months ago
2008
ACM
Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an applicatio...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Scheduling plays a central role in the behavioral synthesis process, which automatically compiles high-level specifications into optimized hardware implementations. However, most ...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
IDEAS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper proposes CADRE (Collaborative Allocation and Deallocation of Replicas with Efficiency), a dynamic replication scheme for improving the typically low data availability ...
FCCM
2009
IEEE
14 years 10 days ago
2009
IEEE
This paper proposes a high performance least square solver on FPGAs using the Cholesky decomposition method. Our design can be realized by iteratively adopting a single triangular...