1461 search results - page 255 / 293 » Comparing the Optimal Performance of Parallel Architectures |
ISSS
2002
IEEE
14 years 1 months ago
2002
IEEE
We present a system-level design and programming method for embedded multiprocessor systems. The aim of the method is to improve the design time and design quality by providing a ...
CORR
2011
Springer
13 years 3 months ago
2011
Springer
Markov Logic Networks (MLNs) have emerged as a powerful framework that combines statistical and logical reasoning; they have been applied to many data intensive problems including...
ICS
2003
Tsinghua U.
14 years 1 months ago
2003
Tsinghua U.
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
CGO
2010
IEEE
14 years 3 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Many P2P systems have been designed without taking into account an important factor: a large fraction of Internet users nowadays are located behind a network address translator (NA...