1461 search results - page 270 / 293 » Comparing the Optimal Performance of Parallel Architectures |
TJS
2008
13 years 8 months ago
2008
Multiple memory models have been proposed to capture the effects of memory hierarchy culminating in the I-O model of Aggarwal and Vitter [?]. More than a decade of architectural a...
TVLSI
2008
13 years 8 months ago
2008
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
CJ
2004
13 years 8 months ago
2004
This paper describes a way to manage the modeling and analysis of Scheduled Maintenance Systems (SMS) within an analytically tractable context. We chose a significant case study h...
TSMC
2002
13 years 8 months ago
2002
This paper describes the dynamic control of a 3 degree of freedom (DOF) finger emulating a human finger for reaching a desired fingertip position in space. The control consists of ...
LCTRTS
2010
Springer
14 years 3 months ago
2010
Springer
Coarse Grain Reconfigurable Architectures (CGRAs) promise high performance at high power efficiency. They fulfil this promise by keeping the hardware extremely simple, and movi...