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» Comparing the Optimal Performance of Parallel Architectures
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ICASSP
2011
IEEE
12 years 11 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...
ICPP
2008
IEEE
14 years 1 months ago
Optimizing JPEG2000 Still Image Encoding on the Cell Broadband Engine
JPEG2000 is the latest still image coding standard from the JPEG committee, which adopts new algorithms such as Embedded Block Coding with Optimized Truncation (EBCOT) and Discret...
Seunghwa Kang, David A. Bader
NAA
2004
Springer
178views Mathematics» more  NAA 2004»
14 years 23 days ago
Performance Optimization and Evaluation for Linear Codes
In this paper, we develop a probabilistic model for estimation of the numbers of cache misses during the sparse matrix-vector multiplication (for both general and symmetric matrice...
Pavel Tvrdík, Ivan Simecek
IPPS
2009
IEEE
14 years 2 months ago
A scalable auto-tuning framework for compiler optimization
We describe a scalable and general-purpose framework for auto-tuning compiler-generated code. We combine Active Harmony’s parallel search backend with the CHiLL compiler transfo...
Ananta Tiwari, Chun Chen, Jacqueline Chame, Mary W...
MICRO
1991
IEEE
85views Hardware» more  MICRO 1991»
13 years 11 months ago
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors
This paper examines two alternative approaches to supporting code scheduling for multiple-instruction-issue processors. One is to provide a set of non-trapping instructions so tha...
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, ...