In this paper we present two new approaches based on genetic algorithms (GA) to reduce power consumption by communication buses in an embedded system. The first approach makes it ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
Learning Deterministic Finite Automata (DFA) is a hard task that has been much studied within machine learning and evolutionary computation research. This paper presents a new met...
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
In this paper, we describe a low power and high speed multiplier suitable for standard cell-based ASIC design methodologies. For the purpose, an optimized booth encoder, compact 2...
Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-se...
This paper reports on a specific food and agribusiness industry project, employing new technological capabilities to better transfer expert knowledge. Knowledge transfer and techn...